Ce diagramme trace l’exécution de LplKernel à un niveau de détail extrême. Il combine les appels de fonctions réels du code source actuel (C/ASM) avec une projection architecturale des implémentations futures (EDF, SASOS, Zero-Syscall) définies dans la Roadmap et le Chapitre 10.
sequenceDiagram
autonumber
%% ==========================================
%% PARTICIPANTS
%% ==========================================
box rgb(30, 30, 30) Hardware & Boot
participant HW as 🖥️ HW (CPU/RAM/NIC/APIC)
participant GRUB as 💿 GRUB (Multiboot)
end
box rgb(10, 40, 80) Kernel Core (Ring 0)
participant Boot as ⚙️ boot.S (ASM)
participant BSP as 🧠 CPU 0 (kernel.c)
participant AP as 🧠 CPUs 1-N (Trampoline)
participant Intr as ⚡ IDT & APIC
participant Sched as ⏱️ Scheduler (EDF)
end
box rgb(60, 20, 80) Kernel Subsystems
participant Mem as 💾 PMM & VMM (SASOS)
participant Alloc as 📦 Allocators (Slab/Arena)
participant Drv as 🔌 PCI & Drivers
participant Net as ⚡ Data Plane (Bypass)
end
box rgb(10, 60, 40) Userspace (Ring 3 - PKey Isolated)
participant LplPlugin as 🎮 LplPlugin (VR Engine)
participant Flakkari as 🌐 Flakkari (UDP Server)
end
%% ==========================================
%% PHASE 1-3: BOOTLOADER AND HIGHER-HALF
%% ==========================================
rect rgb(0, 50, 100)
Note over HW,Boot: Phases 1-3: Boot & Higher-Half Paging (Current)
HW->>GRUB: Power On, POST, BIOS/UEFI Handoff
GRUB->>GRUB: Parse grub.cfg, Load Kernel ELF
GRUB->>Boot: Jump to _start (EAX=0x2BADB002, EBX=Multiboot_Info)
activate Boot
Boot->>Boot: Set up early Page Directory (Identity + 0xC0000000)
Boot->>HW: Enable Paging (CR0, CR3, CR4)
Boot->>Boot: Jump to Higher Half (lea ecx, 4f then jmp ecx)
Boot->>Boot: Setup early kernel stack (esp = stack_top)
Boot->>BSP: call kernel_initialize()
deactivate Boot
activate BSP
end
%% ==========================================
%% PHASE 1-3: BASE ARCHITECTURE
%% ==========================================
rect rgb(20, 60, 120)
Note over BSP,Intr: Phases 1-3: CPU & Interrupts (Current)
BSP->>Drv: serial_initialize(COM1, 9600)
BSP->>BSP: terminal_initialize() & kernel_splash_initialize()
BSP->>BSP: write_multiboot_info(EBX) -> RAM Map
BSP->>BSP: global_descriptor_table_initialize()
BSP->>HW: lgdt [GDT] (Ring 0, Ring 3, TSS)
BSP->>Intr: interrupt_descriptor_table_initialize()
BSP->>Intr: Register isr_stubs (0-47)
BSP->>HW: lidt [IDT]
BSP->>Intr: clock_initialize() (Base timing contract)
BSP->>BSP: cpu_topology_initialize()
end
%% ==========================================
%% PHASE 4: VMM, PMM AND ALLOCATORS
%% ==========================================
rect rgb(50, 0, 100)
Note over BSP,Alloc: Phase 4: Full Memory Subsystem (Current)
BSP->>Mem: paging_initialize_runtime()
Mem->>HW: Flush TLB (invlpg)
BSP->>Mem: kernel_vmm_initialize()
BSP->>Mem: physical_memory_manager_initialize()
Note right of Mem: Initialize Buddy Allocator (PMM Pass 1)
BSP->>HW: advanced_configuration_and_power_interface_madt_initialize()
HW-->>BSP: Return ACPI Tables (LAPIC, IOAPIC, ISO)
BSP->>BSP: numa_policy_initialize()
BSP->>Mem: physical_memory_manager_extend_mapping()
Note right of Mem: Map all RAM discovered by Multiboot (PMM Pass 2)
BSP->>Alloc: kernel_heap_initialize()
Note right of Alloc: Setup Slab Allocator (Size classes)
par High-Level Allocators
BSP->>Alloc: kernel_frame_arena_initialize(16KB)
BSP->>Alloc: kernel_stack_allocator_initialize(16KB)
BSP->>Alloc: kernel_pool_allocator_initialize(64B, 128 obj)
BSP->>Alloc: kernel_pinned_memory_initialize() (DMA-Ready)
end
BSP->>Alloc: kernel_ring_buffer_initialize_ex(SPSC Mode)
Note right of Alloc: Preparation for Zero-Syscall IPC
end
%% ==========================================
%% PHASE 5: MULTICORE & HARDWARE
%% ==========================================
rect rgb(100, 50, 0)
Note over HW,AP: Phase 3 & 5: SMP, APIC & IO Routing (Current)
BSP->>Intr: input_output_advanced_programmable_interrupt_controller_initialize_routing_scaffold()
BSP->>Intr: ioapic_set_isa_route_destination(IRQ1_KBD, Core0)
BSP->>Intr: advanced_pic_timer_backend_late_initialize()
Note right of Intr: Enable x2APIC (MSR 0x830)
BSP->>AP: kernel_smp_try_start_discovered_aps()
loop For each detected CPU (ACPI MADT)
BSP->>HW: Send IPI (INIT)
BSP->>HW: Send IPI (SIPI) with Trampoline vector
activate AP
HW->>AP: Boot Secondary CPU in Real Mode
AP->>AP: ap_trampoline.S (Paging, GDT, Stack)
AP->>AP: ap_startup.c -> ap_spin_wait()
AP-->>BSP: ACK "I am alive"
end
BSP->>Intr: advanced_pic_timer_backend_calibrate_with_pit()
BSP->>Intr: enable_periodic_mode(frequency_hz)
BSP->>BSP: kernel_smoke_batch_run_initialization_tests()
BSP->>Drv: framebuffer_init() (VBE LFB)
end
%% ==========================================
%% VISION PHASE 6-10: FUTURISTIC ARCHITECTURE
%% ==========================================
rect rgb(100, 0, 50)
Note over BSP,LplPlugin: 🚀 FUTURE VISION (Phases 6 to 10 & U1-U5)
%% Phase 6: Scheduling
Note over Sched,Mem: [Phase 6] EDF Scheduler Initialization
BSP->>Sched: scheduler_edf_initialize()
BSP->>Sched: create_kernel_worker_threads()
Sched->>AP: Assign Workers to dedicated cores (NUMA Affinity)
%% Phase 10: SASOS
Note over Mem,LplPlugin: [Phase 10] SASOS & Memory Protection Keys (MPK)
BSP->>Mem: vmm_sasos_enable_global_address_space()
LplPlugin->>Mem: sasos_allocate_pkey_domain()
Mem-->>LplPlugin: Return PKey 0x1
LplPlugin->>HW: wrpkru (Hardware lock in 2 cycles)
%% Phase 8: Network
Note over Drv,Flakkari: [Phase 8] Data Plane Network Bypass
BSP->>Drv: pci_enumerate_and_init_nic()
Flakkari->>Net: network_bypass_map_rx_to_userspace(PKey 0x2)
Net->>Drv: Configure NIC DMA RX Ring -> Pinned RAM (Flakkari)
%% Phase 9: Zero-Syscall IPC
Note over Alloc,LplPlugin: [Phase 9] Interface Zero-Syscall (Ring Buffers)
LplPlugin->>Alloc: ipc_create_zero_syscall_channel(PKey 0x1)
Alloc-->>LplPlugin: Return {SubmissionQueue, CompletionQueue}
end
%% ==========================================
%% RUNTIME: THE "FULLDIVE" LOOP
%% ==========================================
rect rgb(0, 100, 50)
Note over HW,LplPlugin: ♾️ Runtime Loop: Deterministic VR Engine
BSP->>BSP: kernel_main()
par VR Simulation Frame (Zero-Syscall)
LplPlugin->>Alloc: SPSC_Submit(OP_READ_SENSORS)
Note right of LplPlugin: LplPlugin keeps computing (No INT 0x80)
Note over AP: AP CPU dedicated as Worker
AP->>Alloc: SPSC_Poll() -> Detects OP_READ_SENSORS
AP->>Drv: Extract hardware data
AP->>Alloc: SPSC_Complete(Data)
LplPlugin->>Alloc: Read result on next tick
and Network Bypass
HW->>Net: UDP Packet received on NIC
Net->>HW: Automatic DMA (Hardware RSS) to Flakkari RAM
Note right of Flakkari: Zero CPU interrupt. RAM updated by hardware magic.
and Hard Real-Time (EDF)
HW->>Intr: Timer Tick (APIC)
Intr->>Sched: timer_tick_interrupt()
Sched->>Sched: edf_recalculate_deadlines()
opt If VR SLA at risk
Sched->>HW: context_switch_fast(LplPlugin)
Note right of Sched: Strict preemption to guarantee MTP < 20ms
end
end
end
Dictionnaire des fonctionnalités anticipées
Pour rendre ce diagramme « immersif », plusieurs fonctions conceptuelles ont été extrapolées à partir de la Roadmap :
scheduler_edf_initialize(): Point d’entrée de la Phase 6. Remplace le RR par un calcul de deadline absolu (Liu & Layland).vmm_sasos_enable_global_address_space(): Transition vers la Phase 10 (64-bit). Élimine les changements de CR3 entre processus.sasos_allocate_pkey_domain(): Distribue une clé matérielle MPK. Le processus utilise l’instruction assembleurwrpkrupour s’isoler en 2 cycles CPU.network_bypass_map_rx_to_userspace(): Implémentation du Data Plane (Phase 8). Le kernel épingle des frames physiques (kernel_pinned_memory_initialize) et dit à la carte réseau d’y écrire directement.ipc_create_zero_syscall_channel(): Concrétisation de la Phase 9. Alloue un Ring Buffer SPSC partagé entre le Ring 3 et le Ring 0. Le CPU AP (Worker) fait du polling (spin) sur ce buffer, ce qui élimine les coûteux changements de contexte causés parINT 0x80.
LplKernel : architecture d’un moteur déterministe FullDive Version 1.2, juin 2026 Synthèse de multiples rapports de recherche et diagrammes