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Roadmap

One view over three moving parts: the kernel (OSDev phases), the convergence that links the engine into ring-0, and the engine itself. Dependencies that cross from one project into another are drawn as merge links — that's where the two repos meet.

Done 22 In progress 5 Planned 14 Idea 4 | 45 items total
Project: Status:

LplKernel

5 done · 1 active · 8 ahead

The freestanding i686 OS — OSDev learning path, phases 0→11.

Foundations (Phase 0–4)

100%
Status: Done.

Prerequisites & environment

P0

i686-elf cross-toolchain (gcc14/C++23), Makefiles + xmake, QEMU, GDB/VSCode F5.

#toolchain
Status: Done.

Bare-bones kernel

P1

GRUB multiboot, VGA text mode, serial COM1, scrolling, colors, multiboot parsing.

Status: Done.

CPU init & protection

P2

Higher-half at 0xC0000000, boot + runtime paging, GDT (6 segments), TSS loaded. Ring 3 deferred to P9.

Status: Done.

Interrupts, APIC & SMP

P3

IDT/ISR 0–47, PIC remap, dedicated #PF/#GP/#DF handlers, LAPIC/IOAPIC, x2APIC, MADT, AP bring-up (SMP=2 validated).

#smp
Status: Done.

Memory management

P4

PMM (buddy server / free-list client), kmalloc/kfree, slab caches, frame/pool/ring allocators, pinned DMA, VMM range manager.

#memory

Phase 5 · Device drivers

12%
Status: In progress.

Device drivers

P5
35%

PS/2 keyboard (QWERTY/AZERTY layouts) ✓, PCI bus enumeration + BARs ✓. Next: storage (ATA PIO), then USB.

Status: Planned.

e1000 network driver

P5

Intel 82540EM at BAR0 0xFEB80000 (found by the PCI scan). Native replacement for /dev/lpl0 — entry point for the data-plane convergence.

Status: Planned.

Storage & BCI input

P5

ATA PIO first (simplest), then AHCI/NVMe. High-frequency USB/serial polling for the OpenBCI headset with native Notch/bandpass filtering.

Phase 6 · Scheduling

0%
Status: Planned.

Multitasking & scheduling

P6

Context switch (FXSAVE/XSAVE), round-robin then priority, EDF hard real-time (Liu & Layland) for VR guarantees, sync primitives, IPC.

Phase 7–11 · Advanced

0%
Status: Planned.

High-performance networking

P8

Ethernet/ARP/IP/TCP/UDP, then data-plane bypass (DPDK-style), zero-copy DMA NIC→pinned memory, Receive-Side-Scaling across SMP cores.

Status: Planned.

User space & syscalls

P9

Ring 3, ELF loading. Zero-syscall async interface (SPSC submission/completion rings), SASOS single-address-space, PKeys isolation.

Status: Planned.

64-bit, UEFI & shell

P10

Long mode (4-level paging), UEFI boot, interactive shell, newlib/libsupc++ porting.

Status: Idea.

Power management & green computing

P11

C-states (HLT/MWAIT), P-states, tickless kernel (NO_HZ), DVFS driven by the EDF scheduler, clock/power gating. Crucial for BCI/VR hardware.

Convergence

1 done · 0 active · 6 ahead

The two-repo merge: the engine linked natively into ring-0 (Model B, then U1→U5).

Model B · engine in ring-0

50%
Status: Planned.

Engine.cpp reparent off GLFW/sockets

The last deferred Model-B item: the full facade still drags in the net/BCI/GLFW stack and stays host-only. The freestanding render path is already proven via libengine.

Engine convergence (U1–U5)

0%

LplPlugin

10 done · 2 active · 2 ahead

The cross-platform engine — simulation, network, BCI, rendering.

Phase 1–2 · Foundations

100%
Status: Done.

Core engine foundations

1
100%

ECS + kernel ring buffer PoC, CUDA gravity kernel, pinned memory zero-copy. Validated: 62.55 µs latency, 0% loss, 495 pkt/s.

Status: Done.

Architecture refactor & modularization

2
100%

20 flat modules, Make→xmake (C++23, -fno-rtti/-fno-exceptions), Vulkan backend alongside the software rasterizer, engine facade, CUDA physics port.

#architecture

Phase 3 · Simulation & network

70%
Status: In progress.

Simulation & network research

3
70%

Done: authoritative server, client prediction, EntityRegistry, DAG scheduler, double buffering, octree broadphase. Left: SIMD physics, dirty-list, Hermite prediction, 50–200 ms latency tests, anti-tunneling.

Phase 4 · BCI

70%
Status: In progress.

BCI & neurofeedback research

4
70%

Done: OpenBCI Cyton driver, per-channel FFT/PSD, Schumacher R(t), Riemannian δ_R/Mahalanobis, NeuralMetrics. In progress: auto-calibration. Left: LSL outlet, OpenViBE boxes, feedback loop, motor-imagery decoding.

Phase 5 · Massive simulation

20%
Status: Planned.

Massive simulation & infrastructure

5
20%

Done: octree broadphase, AABB narrow-phase, impulse resolution. Target: 100k+ entities @ 60 FPS — GPU streaming, state compression, session RCU, server meshing, NUMA-aware allocators.

Phase 6 · Immersion

0%
Status: Idea.

Total immersion (FullDive)

6

Photorealistic rendering (NeRF or PBR), haptic feedback, spatial audio, custom RTOS for strict determinism, GPUDirect RDMA (NIC→VRAM).

Determinism gates

100%
Status: Done.

gate P6 — rendering & scene

P6
100%

The first cross-ring gate: cube-pile state and image folds identical between the host oracle and the booted kernel.

#parity
Status: Done.

gate P7 — world generation

P7
100%

One recipe, one world: entity count, state, height and biome signatures all fold identically host-side and in ring 0.

Status: Done.

gate P8 — the living world

P8
100%

A simulation that RUNS under contract: population, genome, stigmergy and social folds over a whole ecological run.

Status: Done.

gate P9 — the endless world

P9
100%

Chunked generation with no seams: a chunk generated alone folds like the same chunk generated among its neighbours.

Status: Done.

gate P10 — botany

P10
100%

L-system growth under the same contract: conifer, broadleaf and shrub folds, with segment and leaf counts.

Status: Done.

gate P11 — erasure codes

P11
100%

The first gate whose two sides run DIFFERENT code: the host XORs 128 bits at a time, ring 0 word by word, and the folds must still match — because addition over GF(2) is associative, commutative and free of rounding. The script fails if both sides take the same path.

Status: Done.

gate P12 — the Rosetta plate

P12
100%

Ten opcodes, a reference interpreter, and a specification written in bytes rather than prose. What is folded is that a machine rebuilt FROM the engraving runs the canonical program identically on both targets — a specification sufficient on one and not the other is sufficient for nobody.

Status: Done.

gate P13 — the reconstructed past

P13
100%

A confidence in Fixed32 decides which of two contradictory claims becomes the consensus view, so it is authoritative state: a rounding that differed between targets would give two histories from one corpus. Checked alongside the folds — the losing account is still reachable.

LplAssistant

5 done · 1 active · 1 ahead

The local mind — inference in ring 3, directing a deterministic engine.

Determinism gates

100%
Status: Done.

gate P14 — the mind

P14
100%

A transformer thinking in ring 0, and thinking the same thought as the host: eight-bit weights, Q16.16 activations, an exponential built from a shift and six Taylor terms, rotary angles from CORDIC. Weights, prompt, scores, residual stream, free tokens and grammar-constrained tokens each fold on their own.

Status: Done.

gate P15 — the satellite

P15
100%

The first gate whose consumers will not all be x86: a hosted room node, the kernel's satellite profile and an eventual microcontroller share no register and must still decide the same things about the same audio — when to send, when to stop, whether the wake word was heard, whether the node is hearing itself. Features come from a Haar cascade because a mel filterbank needs cosines and nothing in ring 0 may compute one.

← gate P14 — the mind #parity#audio#power
Status: Done.

gate P16 — agency

P16
100%

One turn of thought, folded stage by stage — and what it folds is a sequence of DECISIONS rather than a computation: which note survived a full memory, which action was reached for first, whether the turn ended in an answer or a question. Identity is data, not a fine-tune; a budget counts work and never milliseconds, because a wall clock makes a replay depend on how fast the machine was that day.

Status: Done.

gate P17 — reasoning

P17
100%

The same turn, with every move chosen by the transformer running in ring 0 under a grammar rebuilt from the world at each step — so an action already tried stops being spellable, and the anti-loop guard lives in the language rather than in a filter. Measured both ways: under grammar, zero illegal actions; the same weights generating unconstrained named a legal action 0 times out of 8.

← gate P16 — agency #parity#agent#inference

Caine · directing a world

80%
Status: In progress.

Caine — the AI as artistic director

60%

The inversion: the model decides WHAT in a few hundred tokens, the deterministic engine decides HOW. Tool surface, JSON-Schema and GBNF grammar derived from one component declaration; deterministic critics instead of a vision model; every act journalled, so a session is undoable and replayable.

Status: Done.

Constrained decoding

100%

The grammar is regenerated every step and only names what is callable now — a tool the world cannot perform is one the sampler cannot spell.

Jarvis · the local mind

0%
Status: Planned.

Jarvis — the local mind

llama.cpp and whisper.cpp behind a process boundary, pgvector memory, deep research with GBNF-constrained tool calls. Inference stays in ring 3 and speaks to the kernel through the data plane.

LplKnowledge

1 done · 1 active · 1 ahead

The library — a corpus the engine can read, and the demon can cite.

Determinism gates

100%
Status: Done.

gate P18 — the corpus

P18
100%

The first gate that folds a TRANSLATION rather than a computation. The canonical corpus of gate P13 is baked into a .lplknow image by a host tool, read back in ring 0, and the history is rebuilt from what came back — so its timeline, chronicle and minority signatures must equal P13's own. An image that opened cleanly and had quietly rounded one confidence would pass every other check, and the consequence would be a different consensus about how a king died.

Alexandrie · the library

18%
Status: In progress.

The corpus and its extraction

35%

Every algorithm the project rests on, traced back to the report that argued for it and forward to the code that implements it — the reverse index the book will be written from.

#research
Status: Planned.

A library the engine can read

A baked, bounded reader on the ring-0 side of the reader/writer line, so a world can cite what it was built from.

This roadmap is a synthesized cross-project view. The exhaustive, item-by-item checklists live in the repos: LplKernel/docs/ROADMAP.md and the LplPlugin wiki (Roadmap, Implementation-Status, Future-Ideas).